Dear folks,
i want to modulate a signal with the maximum cycle time of the dio bridge, around ~2.5ms. (RevPiIOCycle is 2, cropped integer value)
ATM im counting the RTC ticks in a main while loop, but hence its not synchronized, there is a periodical gap, where my output signal is one cylce longer.
Therefore i need to be synchronized with the RevPi IO Cycle, but there is no interrupt or other possibility to arrange that behavior, right?
Thanks for your help in advance.
Signal modulation with max cycle time
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AthanasiusKircher
- Posts: 2
- Joined: 18 Aug 2021, 14:05
Re: Signal modulation with max cycle time
As annotation i also already tried:
-connecting the output with an input pin, and use that with a flipflop signal as trigger: always change the output signal, when the input signal changes. this leads to flipflop signals with ~7.5ms each. So 3x cycle time
-the python library RevPiModIO: the minimum cycle time i can adjust is 5ms.
But the internal loop of the RevPiModIO in the helper.py script, generated by the ProcImageWriter is also not synchronized with the Revpi IO Cycle.
Thats why there is also a periodical gap where the signal length is 7.5ms and not 5ms
-connecting the output with an input pin, and use that with a flipflop signal as trigger: always change the output signal, when the input signal changes. this leads to flipflop signals with ~7.5ms each. So 3x cycle time
-the python library RevPiModIO: the minimum cycle time i can adjust is 5ms.
But the internal loop of the RevPiModIO in the helper.py script, generated by the ProcImageWriter is also not synchronized with the Revpi IO Cycle.
Thats why there is also a periodical gap where the signal length is 7.5ms and not 5ms
Last edited by AthanasiusKircher on 18 Aug 2021, 18:10, edited 1 time in total.
